1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor wafers. More particularly, the invention relates to an apparatus and method for employing nitrogen oxide (NO) or N2O gases to dope silicon dioxide in a furnace at high temperatures to form oxides and oxynitrides layers on a semiconductor for gate dielectrics.
2. Description of Related Art
The ability to use silicon dioxide (SiO2) as the gate dielectric material becomes extremely difficult for thickness (tox) less than twenty (20) angstroms (Å). Thickness as small as 20 angstroms are required for device scaling with channel lengths less than 0.25 microns (μm). For thickness less than twenty angstroms, leakage currents may approach 1 A/cm2. This is significant when compared to leakages on the order of 1(10−12) A/cm2 for thickness tox greater than 40 angstroms. Thus having a thickness on the order of twenty angstroms may produce prohibitive power consumption of the transistors in the off-state, and reliability concerns through lifetime degradation, i.e., device lifetimes less than ten (10) years.
The leakage current is caused by direct tunneling of electrons from the polysilicon gate electrode through the gate oxide. Boron from the doped poly-silicon gate easily penetrates the thin SiO2 layer causing large Vt shifts and more reliability problems. Boron doped poly-silicon gate electrodes are required to avoid depletion effects which will also cause large Vt shifts and higher threshold voltages. Silicon oxynitrides (SiOxNy) or nitrogen (N) doped SiO2 have been chosen by most integrated circuit chip manufacturers as the material of choice to replace SiO2 for gate dielectrics in the thickness range of 15 to 20 angstroms. The beneficial effects of nitrogen incorporation are dependent upon the magnitude of the doping and the distribution of the doping profile relative to both the Si/SiO2 interface and the poly-silicon gate/SiO2 interface. If the nitrogen doping is engineered correctly, leakage current and boron penetration can be reduced, while minimizing or negating the impact on threshold voltage Vt and channel electron mobility. Additionally, hot-electron defect generation in the silicon channel can be reduced by nitrogen gettering of hydrogen (H). These effects make scaling the gate dielectric down to fifteen (15) angstroms viable, while minimizing the impact on process integration that would occur by changing the gate dielectric to a high dielectric constant (K) material system; the high-K material being different material than the SiO2. The ability to correctly engineer the nitrogen dopant profile is absent in the prior art.
Oxides and oxynitrides for gate dielectrics are typically grown in atmospheric (or reduced pressure) furnaces, where the gas is pre-combusted through a torch injector pre-tube outside of the main process tube. The resultant product is then delivered to the main process tube for reaction with wafers that are pre-processed up to the gate dielectric layer. Typical torch combustion chambers are engineered to preheat gas up to 850° C. for combustion of O2 and H2 to form H2O and O2. H2O is a critical reactant for wet oxidation in the formation of high quality gate oxides, and has been used extensively as such by the semiconductor industry. The torch is also used to combust chlorine containing sources to provide high purity atomic chlorine that is used as a metal getterer in the furnace process chamber which, along with nitrogen oxide (NO), are the two gases that can be used to thermally grow or anneal high quality oxynitride films. However, torches have not been engineered for N2O combustion. For example, in U.S. Pat. No. 6,017,791, issued to Wang, et al., entitled, “MULTI-LAYER SILICON NITRIDE DEPOSITION METHOD FOR FORMING LOW OXIDATION TEMPERATURE THERMALLY OXIDIZED SILICON NITRIDE/SILICON OXIDE (NO) LAYER,” a method for forming a silicon nitride/silicon oxide (NO) layer within a microelectronics fabrication was introduced. In order to form these layers, Wang uses two deposition methods within the same deposition reactor chamber, with the first deposition method separated from the second deposition method by a vacuum purge of the deposition reactor chamber to assure that the second silicon nitride layer is formed as a discrete silicon nitride layer upon the first silicon nitride layer. Each of the nitride layers in the Wang art are formed through a chemical vapor deposition (CVD) process. By implementing a higher temperature outside the main process tube (chamber), the instant invention eliminates, among other things, the vacuum purge of the deposition reactor chamber.
Nitrogen oxide is not typically used since it requires additional safety apparatus due to its toxicity. It can also produce certain undesirable electrical properties of the device, such as low electron channel mobility, large voltage threshold shifts, and hot-electron degradation effects.
The present invention introduces a thermal nitrogen dopant tuner and its ability to make use of the N2O decomposition mechanisms to fabricate transistors with thickness in the ten to twenty angstrom regime.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an apparatus and method for utilizing N2O decomposition mechanisms to make transistors with thickness as small as ten to twenty angstroms.
It is another object of the present invention to provide an apparatus and method for using SiO2 as a gate dielectric material for thickness on the order of 10-20 Å.
A further object of the invention is to provide an apparatus and method for having a substrate with a gate dielectric thickness less than 20 Å without producing prohibitive power consumption due to leakage current losses.
It is yet another object of the present invention to provide an apparatus and method for developing nitrogen doped SiO2 substrate layers to replace SiO2 layers as gate dielectrics with thickness on the order of 10-20 Å.
Another object of the invention is to provide an apparatus and method for reducing leakage current and boron penetration of the SiO2 layer while negating the impact on threshold voltage and channel electron mobility.
A further object of the invention is to provide an apparatus and method for scaling gate dielectrics down to the 10-20 Å regime while minimizing the impact on process integration.
Still other advantages of the invention will in part be obvious and will in part be apparent from the specification.